1. Field of the Invention
The present invention relates to the field of sample-and-hold circuits. In particular, the present invention relates to sample-and-hold circuits for use in analog-to-digital conversion systems with a very high sampling rate.
2. Discussion of Related Art
As is well known in the art, settling of the input signal of an analog-to-digital converter during the sampling phase is critical to the performance of the analog-to-digital conversion. Preferably, such settling should be performed below one quarter of a least significant bit voltage of an analog-to-digital converter to provide a margin for the settling of the analog-to-digital converter input circuitry, e.g. the analog latch within a comparator bank.
An example of a known analog-to-digital conversion system is shown in FIG. 1. The analog-to-digital conversion system 100 includes a closed-loop driving amplifier 102, which has a gain, and a sample-and-hold switch 104. The gain of the driving amplifier 102 is defined by the ratio of the feedback resistors R2 and R1 and the sample-and-hold switch 104 can be built using a single NMOS transistor that is controlled by a sample clock 105. The input capacitance of the analog-to-digital converter 106 can perform as a storage capacitor during the hold phase. If the input signal of the sample-and-hold switch 104 changes within the hold period, settling to a new value is required in the sampling period. The voltage step that has to be performed between two adjacent samples can be as high as the full-scale analog-to-digital converter voltage. At very high sampling rates, it is not possible to settle such a voltage step using the closed-loop driving amplifier 102 driving the sample-and-hold switch 104 because of the limited unity gain bandwidth of the amplifier 102. The unity gain bandwidth has to be approximately an order of magnitude higher than the sample clock frequency if settling to one quarter of the least significant bit voltage of the analog-to-digital converter is to be obtained. The situation becomes even worse if the amplifier 102 has to provide gain because the closed-loop corner frequency, which is defining the settling time constant, decreases linearly with the gain compared to the unity gain bandwidth of the amplifier. Thereby, the maximum possible sampling rate using a sample-and-hold driver with an amplifier in a closed-loop configuration is limited.
Another example of an analog-to-digital conversion system that uses a closed-loop amplifier is shown in FIG. 2. The analog-to-digital conversion system 200 includes a closed-loop driving amplifier 202 that has an open-loop buffer circuit, such as an NMOS source follower 204, positioned at the output of the amplifier 202 to perform high-speed settling. The open-loop buffer circuit has gain-variations caused by technology variations during processing. Gain variations can be controlled by incorporation of a replica buffer, such as an additional NMOS source follower 206, in the feedback branch of the closed-loop amplifier 202. The replica buffer must be operated at the same current density as the output buffer. An implementation using a scaling factor N for both the (W/L)-ratio and the current-source currents can be chosen. Harmonic distortion in the output buffer, which can be due to variations of the threshold voltage of the source follower having a body effect, can be corrected for by the same replica buffer approach.
During operation of the analog-to-digital conversion system 200, a change of the output signal at nodes vom and vop up to the full-scale value of the analog-to-digital converter is possible between two adjacent samples at input signal frequencies close to half the sampling frequency. Therefore, during switching of the sample and hold switch 208 from hold to sampling phase, large voltage transients occur at voutm and voutp that have to be settled within half the clock phase. These transients cause the gate potential of the source-follower 204 to change due to a kickback effect. Because the gate of the source-follower buffer 204 is tied to the output gain nodes vgainm and vgainp of the gain-setting amplifier 202, a settling process of the closed loop amplifier 202 is triggered. During this settling process the output voltage at the gain nodes vgainm and vgainp of the core amplifier and hence the gate voltage of the source-follower 204 driving the sample and hold switch 208 will show ringing. This will alter the output voltage voutm and voutp of the sample and hold switch 208. Hence, at very high sampling rates settling to a quarter of a least significant bit voltage within the sampling period will be distorted and may not be accurately performed if the kickback can not be reduced and/or the ringing can be avoided. One way to avoid ringing during the mentioned settling process is to design the gain-setting amplifier for a high phase-margin. However, this limits the maximum signal bandwidth that can be processed by the gain-setting amplifier because the unity gain bandwidth has to be reduced.
Due to the level-shift performed by the NMOS source follower the common-mode voltage at the gain nodes vgainm and vgainp is very high. Hence it is not possible to achieve a high DC gain of the amplifier at these nodes at low supply voltages below 2 V because the required drain-source voltages for the pull-up current-source, which is part of the amplifier 202 and can be a DC current source or the output of a current mirror controlled e.g. by the amplifier""s input stage, is not high enough to use cascode transistors in order to improve the output impedance of the source. The high gain is required in order to set the gain of the total circuit by the ratio of the feedback resistors R2 and R1 and to achieve low harmonic distortion. If the amplifier""s gain is not sufficiently high, i.e.  greater than 50 dB, gain variations due to process variations will alter the total gain of the system.
A high gain might be obtained in case both the output voltage range and the output common-mode voltage are significantly reduced. However, a limited output range results in a limited analog-to-digital converter full-scale range, which immediately reduces the analog-to-digital converter""s performance due to analog noise.
In summary, prior analog-to-digital conversion systems that have a sample-and-hold switch driven by closed-loop amplifiers have several shortcomings. For example, such analog-to-digital conversion systems have longer settling times at maximum input voltage steps that occur at input signal frequencies close to the Nyquist frequency, i.e. half the sampling frequency. During the sampling phase, at very high sampling rates a closed-loop amplifier circuit is not capable of settling a full-scale voltage step at the output of the sample-and-hold switch to below one quarter of an analog-to-digital converter least significant bit voltage at typical analog-to-digital converter resolutions up to 6 bit and a differential full-scale voltage of up to 1V peak-to-peak. Such large signal voltage steps occur at input signal frequencies close to the Nyquist frequency. Accordingly, if settling to a quarter of an analog-to-digital converter least significant bit at typical analog-to-digital converter resolutions up to 6 bit and a differential full-scale voltage of up to 1V peak-to-peak is required to provide headroom for the settling of the first analog latch stage of the analog-to-digital converter, the maximum sampling rates are limited.
Another problem of analog-to-digital conversion systems that use a closed-loop amplifier and single open-loop source-followers to drive the sample-and-hold switch is that for signal frequencies near the Nyquist frequency, incomplete settling of maximum input voltage steps can occur due to ringing of the gain-setting amplifier caused by the kickback onto the amplifier""s gain-node. Incomplete settling introduces sampling errors and can be the cause of harmonic distortion of the analog-to-digital conversion system. If ringing is avoided by design of the gain-setting amplifier for higher phase margin, the maximum input signal-bandwidth is limited.
Furthermore, a high gain at the output of the amplifier renders it difficult to obtain a high DC gain at low supply voltages below 2 V due to the high common-mode voltage level at the amplifier""s gain nodes. Thereby, the total gain of the system can vary with process variations. If the output voltage range and common-mode voltage are significantly reduced to enable circuitry in the amplifier that provides a higher DC then the analog-to-digital converter""s performance will suffer due to the higher analog noise with respect to the full-scale range.
One aspect of the present invention regards a sample-and-hold system that includes a first source follower having an input and an output and a second source follower that includes an input connected in series with the output of the first source follower. A sample-and-hold switch connected to an output of the second source follower.
A second aspect of the present invention regards an analog-to-digital conversion system that includes an amplifier and a sample-and-hold system. The sample-and-hold system includes a first source follower having an input connected to an output of the amplifier, a second source follower that includes an input connected in series with an output of the first source follower and a sample-and-hold switch connected to an output of the second source follower. An analog-to-digital converter connected to an output of the sample-and-hold switch.
Each of the above aspects of the present invention provides the advantage of allowing for higher sampling rates and improved settling for sample-and-hold circuits used in analog-to-digital conversion systems.
Each of the above aspects of the present invention provides the advantage of sensing and correcting gain variations in sample-and-hold circuits used in analog-to-digital conversion systems.
Each of the above aspects of the present invention provides the advantage of operation at low supply voltages below 2 V.
The present invention, together with attendant objects and advantages, will be best understood with reference to the detailed description below in connection with the attached drawings.